The present invention relates generally to a phase change random access memory (PRAM), and more particularly to a PRAM including dummy cells and a layout method of the same.
In general, when forming memory cells of a PRAM, a cell array may be formed by repeated arrangement of memory cell strings including diodes formed by selective epitaxial growth.
That is, in a single cell array, an 8-bit cell string may be arranged in a global wordline direction and a global row decoding line connected to a global row decoder (global X-decoder) together with the 8-bit cell strings may be arranged in a bitline direction.
Herein, since the global row decoding line is used for the purpose of transferring bias to a gate of a local switch transistor placed between the cell arrays, the global row decoding line is not connected with memory cells. Further, in order to make process conditions similar to those of the memory cell, a dummy cell is formed below the global row decoding line.
As shown in FIG. 1, a dummy cell string 12 having the same structure as the 8-bit memory cell string may be formed below the global row decoding line GXDEC to make the condition similar to the memory cell because the global row decoding line GXDEC is formed in upper layer of bitlines BL0˜BL7 (i.e. in the same layer as the global wordline). Herein, the global decoding line GXDEC describes a line that transfers a signal for selecting global wordline outputted from the global row decoder.
A lower via 14 is formed on either side of the dummy cell string 12 on a dummy active region 10. In order to interrupt electrical connection between the global row decoding line GXDEC and the dummy cell string 12, a via for electrically connecting the lower via 14 and the global row decoding line GXDEC is not formed as marked by a dotted circle 16 in FIG. 1. Also, the dummy active region 10 is kept in a ground voltage (VSS) state.
However, since the dummy cell string 12 has, like other memory cells, a structure that is respectively electrically connected with the bitlines BL0˜BL7, there is a problem that when one bitline BL is selected, current Ipara may flow to the dummy active region 10 through a dummy cell electrically connected to the selected bitline BL. For example, when bitline B5 is selected, the current Ipara may flow to the dummy active region 10 through the dummy cell electrically connected to the selected bitline BL5.
That is, when one bitline BL5 is selected, a predetermined voltage (generally, a boost voltage VPP) is supplied to the selected bitline BL5 and thus data is accessed in the memory cell. At this time, since the dummy active region 10 below the global row decoding line GXDEC is in the ground (VSS) state, current Ipara flows from the bitline BL5 to the dummy active region 10 through the dummy cell connected with the selected bitline BL5.
This parasitic current Ipara passing through the dummy cell may affect data state according to phase change of the memory cell. Therefore, this is problematic in that a sense amplifier that senses and amplifies the data may malfunction, resulting in difficulty in distinguishment of ‘1’ and ‘0’ in the data.
Also, as no upper via is formed on the dummy cell string 12, a pattern collapse may occur at the two outermost bitlines BL0, BL7 of the bitlines BL0˜BL7.
The pattern collapse will be described in more detail with respect to FIG. 2. As the bitlines BLO˜BL7 are disposed with equal spacing therebetween, none of the bitlines BL1˜BL6 collapse.
In a memory cell region 20 in which memory cell strings (not shown) are disposed, as upper vias 24 electrically connecting the memory cell strings and global wordlines GWL0˜GWL7 are formed at the outside of the two outermost bitlines BL0, BL7, the pattern collapse of the two bitlines BL0, BL7 does not occur.
However, in a dummy cell region 22, in which dummy cell strings (not shown) are disposed, the upper vias are not formed at the outside of the two outermost bitlines BL0, BL7 in order to electrically isolate the dummy cell string and a global row decoding line GXDEC, this results in problems in that the two bitlines BL0, BL7 may collapse in the direction shown in FIG. 2.
When the bitline (for example, BL0) collapses, an electrical short 26 between the upper via 24 and the bitline BL0 may occur, which results in an unwanted electrical connection between the global wordline (for example, GWL7) and the bitline BL0.
When the global wordline GWL7 and the bitline (for example, BL0) are electrically connected due to the collapse of the bitline BL0, there is a problem in that a data access error may occur because a direct current path is formed between the global wordline GWL7 and the bitline BL0.
Also, upon data access, for example, when the global wordline GWL7 is activated to a ground voltage VSS level and the bitline BL0 is activated to a boost voltage VPP level, there is a problem that consumption of the boost voltage VPP may be rapidly increased due to electrical short between the global wordline GWL7 and the bitline BL0.
Further, upon standby, for example, when the global wordline GWL7 is in an inactivated state at a boost voltage VPP level and the bitline BL0 is in an inactivated state at a ground voltage VSS level, there is a problem in that a leakage current may be rapidly increased due to electrical short between the global wordline GWL7 and the bitline BL0.
In order to solve these problems, a solution of adding a dummy line between the bitline disposed at the outside and the upper via may be considered. However, this proposed solution brings about additional problems, including an increase in the area of the cell array due to the addition of the dummy line.
Alternatively, regions of the outermost bitlines BL0, BL7, which correspond to a predetermined global wordline GWL4, may be extended toward the upper via 30.
However, extend the bitline sufficiently to prevent the pattern collapse is difficult because of the space between the bitline BL0, BL7 and the upper via 30, therefore there is a large possibility of electrical short between the bitline BL0, BL7 and the upper via 30 when the bitline BL0, BL7 is extended toward the upper via 30.